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Design for Manufacturability [libro electrónico] : ; From 1D to 4D for 90-22 nm Technology Nodes / by Artur Balasinski.

Por: Tipo de material: TextoTextoDetalles de publicación: New York, NY : Springer New York : Imprint: Springer, 2014.Descripción: viii, 278 p : ilTipo de contenido:
  • text
Tipo de medio:
  • computer
Tipo de soporte:
  • online resource
ISBN:
  • 9781461417613
Tema(s): Formatos físicos adicionales: Printed edition:: Sin títuloClasificación LoC:
  • TK7888.4
Recursos en línea:
Contenidos:
Preface -- Classic DfM: from 2D to 3D -- DfM at 28 nm and Beyond -- New DfM Domain: Stress Effects -- Conclusions and Future Work.
Resumen: This book explains integrated circuit design for manufacturability (DfM) at the product level (packaging, applications) and applies engineering DfM principles to the latest standards of product development at 22 nm technology nodes.  It is a valuable guide for layout designers, packaging engineers and quality engineers, covering DfM development from 1D to 4D, involving IC design flow setup, best practices, links to manufacturing and product definition, for process technologies down to 22 nm node, and product families including memories, logic, system-on-chip and system-in-package. ·         Provides design for manufacturability guidelines on layout techniques for the most advanced, 22 nm  technology nodes; ·         Includes information valuable to layout designers, packaging engineers and quality engineers, working on memories, logic, system-on-chip and system-in-package;  ·         Offers a highly-accessible, single-source reference to information otherwise available only from disparate sources; ·         Helps readers to translate reliability methodology into real design flows.
Tipo de ítem: Libro electrónico Lista(s) en las que aparece este ítem: Ebooks
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Preface -- Classic DfM: from 2D to 3D -- DfM at 28 nm and Beyond -- New DfM Domain: Stress Effects -- Conclusions and Future Work.

This book explains integrated circuit design for manufacturability (DfM) at the product level (packaging, applications) and applies engineering DfM principles to the latest standards of product development at 22 nm technology nodes.  It is a valuable guide for layout designers, packaging engineers and quality engineers, covering DfM development from 1D to 4D, involving IC design flow setup, best practices, links to manufacturing and product definition, for process technologies down to 22 nm node, and product families including memories, logic, system-on-chip and system-in-package. ·         Provides design for manufacturability guidelines on layout techniques for the most advanced, 22 nm  technology nodes; ·         Includes information valuable to layout designers, packaging engineers and quality engineers, working on memories, logic, system-on-chip and system-in-package;  ·         Offers a highly-accessible, single-source reference to information otherwise available only from disparate sources; ·         Helps readers to translate reliability methodology into real design flows.

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